Ultra high gain bidirectional dc to dc converter

ABSTRACT

A bi-directional DC voltage converter includes a controller, controlled switches, inductors, and capacitors to accomplish DC voltage conversion with minimal input current ripple and high efficiency. The controller is operable in a boost mode in which the switches are independently controlled to convert low-voltage DC power to high-voltage DC power. The controller is operable in a buck mode in which the switches are independently controlled to convert high-voltage DC power to low-voltage DC power.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application62/987,811, filed on Mar. 10, 2020, the entire contents of which isincorporated herein in its entirety.

BACKGROUND

High voltage gain direct current (DC) to DC converters are employed inmany electrical systems, including but not limited to: (i) integrationof photovoltaic (PV) power sources with an electrical power grid, (ii)PV or battery powered alternating current (AC) sources also known asuninterrupted power supplies, (iii) battery powered electric vehicles(EV), (iv) fuel cell powered electric vehicles, and (iv) hybrid electricvehicles (HEV).

In many of the above applications, a high voltage (Voltage>200 V DC) ispreferred for the common DC bus, as higher voltages result in more powertransfer at higher efficiency in a compact size. The output voltagelevel of input energy sources for the above applications is typicallylow (usually 24 V to 48 V). The low voltage power supplied by the inputenergy sources is typically converted to a high voltage power (e.g. 110V to 400 V). For example, a low input voltage level (say 12 V or 24 VDC) is preferred in electric vehicles, hybrid electric vehicles and fuelcell powered vehicles. A low input voltage level often results in theuse of compact batteries and paralleling of batteries to get high powerdensity. In these applications, high voltage (110 V AC or 220 V AC)motors are preferred because high voltage motors have higherefficiencies, higher power, and smaller overall size compared to lowvoltage motors. In heavy vehicles, motors with still higher voltagerating (e.g. 400 V AC) are preferred, requiring a DC bus voltage of theorder of 800 V. Similarly, in PV systems, batteries in the range 12 V to24 V are preferred. In PV applications, output loads match a power gridvoltage, which (depending on region) may be on the order of 220 V singlephase AC, 400 V line-to line (L-L) three phase AC, or comparable, whichrequires DC bus voltages of 400 V or 800 V. Any of the above systems mayhave the capacity of regeneration, i.e. allowing energy flow from anoutput load to an input source, in addition to normal energy flow froman input source to output load. Therefore, all such systems require highvoltage gain (step up or boost) from the input source to the outputload, and at the same time require a high voltage reduction ratio (stepdown or buck) from the output load to the input source during reverseenergy flow or regeneration.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments in accordance with the present disclosure will bedescribed with reference to the drawings, in which:

FIG. 1 is a simplified functional block diagram of an example electricvehicle drive system;

FIG. 2 shows a circuit diagram of a DC/DC converter, in accordance withvarious embodiments;

FIG. 3 illustrates the DC-DC converter of FIG. 2 in a step-up or boostmode of operation;

FIGS. 4 a through 4 c illustrate gating pulses for three types namelyPWM1, PWM2 and PWM3 operation of the DC-DC converter of FIG. 2 in thestep-up or boost mode of operation;

FIG. 5 is a graphical illustration showing steady state voltage gainversus duty cycle for the step-up or boost mode of operation of thecircuit of FIG. 3 ;

FIG. 6 illustrates the DC-DC converter of FIG. 2 in a step-down or buckmode of operation;

FIGS. 7 a and 7 b illustrate gating pulses for the two types namely PWM1and PWM2 operation of the DC-DC converter of FIG. 2 in the step-down orbuck mode of operation;

FIG. 8 is a graphical illustration showing the steady-state buck voltagegain over a duty cycle for the step-down or buck mode of operation ofthe circuit of FIG. 6 ;

FIGS. 9 a and 9 b illustrate circuit status in PWM1 operation for the0≤t<DT interval in the boost mode, with FIG. 9 a showing the completecircuit and FIG. 9 b showing the equivalent circuit based on the switchconfiguration;

FIG. 10 a and 10 b illustrate circuit status in PWM1 operation for theDT≤t≤(1−D)T interval in the boost mode, with FIG. 10 a showing thecomplete circuit and FIG. 10 b showing the equivalent circuit based onthe switch configuration;

FIG. 11 a shows gate pulses at each respective switch S₁, S₂, S₃, S₄ andS₅ in a simulation of the PWM1 operation in the boost mode;

FIG. 11 b shows voltage wave forms v_(L1), v_(L2), v_(C1), v_(C2), andv_(L) and v_H in the simulation of the PWM1 operation in the boost mode;

FIG. 11 c shows voltage wave forms of v_(s1), v_(s2), v_(s3), v_(s4),and v_(s5) in the simulation of the PWM1 operation in the boost mode;

FIG. 11 d shows current wave forms i_(L), i_(L1), i_(L2), i_(H) andi_(CH) in the simulation of the PWM1 operation in the boost mode;

FIG. 11 e shows current wave forms i_(S1), i_(S2), i_(S3), i_(S4) andi_(S5) through the switches in the simulation of the PWM1 operation inthe boost mode;

FIG. 12 a shows gate pulses at each respective switch S₁, S₂, S₃, S₄ andS₅ in a simulation in the PWM2 operation in the boost mode;

FIG. 12 b shows voltage waveforms v_(L1), v_(L2), v_(C1), v_(C2), andv_(L) and v_H in the simulation in the PWM2 operation in the boost mode;

FIG. 12 c shows voltage wave forms of v_(s1), v_(s2), v_(s3), v_(s4) andv_(s5) in the simulation in the PWM2 operation in the boost mode;

FIG. 12 d shows current wave forms i_(L), i_(L1), i_(L2), i_(H) andi_(CH) in the simulation in the PWM2 operation in the boost mode;

FIG. 12 e shows current wave forms i_(S1), i_(S2), i_(S3), i_(S4) andi_(S5) through the switches in the simulation in the PWM2 operation inthe boost mode;

FIGS. 13 a and 13 b illustrate circuit status in PWM1 operation for the0≤t<DT interval in the buck mode, with FIG. 13 a showing the completecircuit and FIG. 13 b showing the equivalent circuit based on the switchconfiguration;

FIGS. 14 a and 14 b illustrate circuit status in PWM1 operation for theDT≤t≤(1−D)T interval in the buck mode, with FIG. 14 a showing thecomplete circuit and FIG. 14 b showing the equivalent circuit based onthe switch configuration;

FIG. 15 a shows gate pulses at each respective switch S₁, S₂, S₃, S₄ andS₅ in a simulation in the PWM1 operation in the buck mode;

FIG. 15 b shows voltage wave forms v_(s1), v_(s2), v_(s3), v_(s4),v_(s5) in the simulation in the PWM1 operation in the buck mode;

FIG. 15 c shows voltage wave forms v_(H), i_(H), i_(L1), and i_(L2) inthe simulation in the PWM1 operation in the buck mode;

FIG. 15 d shows current wave forms i_(L), v_(L1), v_(L2), v_(C1), andv_(C2) in the simulation in the PWM1 operation in the buck mode;

FIG. 15 e shows current wave forms i_(S1), i_(S2), i_(S3), i_(S4) andi_(S5) through the switches in the simulation in the PWM1 operation inthe buck mode;

FIG. 16 a shows gate pulses at each respective switch S₁, S₂, S₃, S₄ andS₅ in a simulation in the PWM2 operation in the buck mode;

FIG. 16 b shows voltage wave forms of v_(s1), v_(s2), v_(s3), v_(s4) andv_(s5) in the simulation in the PWM2 operation in the buck mode;

FIG. 16 c shows voltage wave forms v_(H), v_(L), i_(L1), i_(L2), andi_(H) in the simulation in the PWM2 operation in the buck mode;

FIG. 16 d shows current wave forms i_(L), v_(L1), v_(L2), v_(C1), andv_(C2) in the simulation in the PWM2 operation in the buck mode;

FIG. 16 e shows current wave forms i_(S1), i_(S2), i_(S3), i_(S4) andi_(S5) through the switches in the simulation in the PWM2 operation inthe buck mode;

FIG. 17 shows the actual or non-ideal gain of the DC-DC converter ofFIG. 2 in configuration PWM1 in boost mode;

FIG. 18 shows the actual or non-ideal gain of the DC-DC converter ofFIG. 2 in configuration PWM2 in boost mode;

FIG. 19 shows the actual or non-ideal gain of the DC-DC converter ofFIG. 2 in configuration PWM1 in buck mode;

FIG. 20 shows the actual or non-ideal gain of the DC-DC converter ofFIG. 2 in configuration PWM2 in buck mode;

FIG. 21 diagrammatically shows an example of a unidirectional high gainDC to DC boost converter, in accordance with various embodiments; and

FIG. 22 diagrammatically shows an example of a unidirectional high gainDC to DC buck converter, in accordance with various embodiments.

DETAILED DESCRIPTION

In the following description, various embodiments will be described. Forpurposes of explanation, specific configurations and details are setforth in order to provide a thorough understanding of the embodiments.However, it will also be apparent to one skilled in the art that theembodiments may be practiced in other configurations, or without thespecific details. Furthermore, well-known features may be omitted orsimplified in order not to obscure the embodiment being described.

Power ratings and battery voltages for EV/HEVs vary depending on theapplication. For example, power ratings for EV/HEVs generally vary from300 W to 400 kW. At a lower end of the spectrum, the power rating for anelectric scooter rating is typically a fraction of a kilowatt. The powerratings for cars are typically in a range from 3 kW to 110 kW. The powerratings for trucks are typically in a range from 100 kW to 390 kW. Thevoltage ratings for EV/HEVs typically vary depending upon the drivesystem employed. Battery voltages for EV/HEVs is typically in a rangefrom of about 24 V to 96 V where lower voltage is preferred.

FIG. 1 is a simplified functional block diagram of an electric vehicle10 that includes DC-DC converters 12, a DC bus 14, a DC-AC converter 16,a drive system 18, a battery 20, and a super capacitor 22. The DC-DCconverters 12 are configured as described herein. The drive system 18includes an AC traction motor 24. In the illustrated embodiment, thedrive system 18 is a front-wheel drive system. The drive system 18,however, can be any suitable type of drive system such as four-wheeldrive, two-wheel drive, rear-wheel drive, all-wheel drive (in the wheeland near the wheel) or any other drive train used in battery-operatedelectric vehicles and hybrid electric vehicles.

FIG. 2 shows a schematic diagram of a bidirectional DC-DC converter 12,according to various embodiments. The DC to DC converter 12 hasbidirectional energy flow capacity. In a forward power flow mode (i.e.,energy transfer from input source to output load) the DC-DC converter 12acts as STEP UP or BOOST converter. In many embodiments, the DC-DCconverter 12 is configured to produce a voltage ratio gain greater than5.8, which is much higher that what can be achieved by many existing DCto DC converters. In a reverse power flow mode (i.e. energy transferfrom output to input), the DC-DC converter 12 acts as STEP DOWN or BUCKconverter with high buck (or voltage reduction) ratio of Gain <1/5.8. Inmany embodiments, the DC-DC converter 12 is configured to produce a stepdown ratio that is significantly greater than what can be achieved bymany existing bidirectional converters.

In addition to having bidirectional power flow capability, embodimentsof the DC-DC converter 12 can have the following attractive features:

-   -   a voltage gain (ratio of output voltage to input voltage) for        boost operation of at least 5.83;    -   for step down or buck operation, an output voltage step-down        gain can have a maximum value of 0.18;    -   a low number of passive circuit components, such as only two        inductors and three capacitors;    -   a low number of switches, such as only five active switches if        the DC-DC converter 12 is used as bidirectional converter, and        can have only two switches if the DC-DC converter 12 is used as        unidirectional boost converter;    -   the input and output terminals can share the same ground, and        the main active switches can share the same common ground;    -   compared to many existing DC-DC converters, the DC-DC converter        12 has a low input current ripple, which is advantageous when        the power source is a battery; and    -   compared to many existing DC-DC converters, the DC-DC converter        12 has increased efficiency due to employing fewer passive        elements and fewer conducting switches.

Operating Principle of the Converter

In the embodiment illustrated in FIG. 2 , the DC-DC converter 12includes an energy transfer control circuit (12CIR) and a controller(12CON). The energy transfer control circuit (12CIR) includes fiveswitches (S₁, S₂, S₃, S₄, S₅), input terminals 26, 28, output terminals30, 32, switch body diodes 34, 36, 38, 40, 42, inductors (L₁, L₂),output capacitor (C_(H)), input capacitor (C_(L)), and circuitcapacitors (C₁, C₂). The controller (12CON) is configured to control thefive switches (S₁, S₂, S₃, S₄, S₅) as described below to achievereversible energy transfer between the input terminals 26, 28 and theoutput terminals 30, 32. The controller (12CON) can have any suitableconfiguration for controlling the five switches (S₁, S₂, S₃, S₄, S₅). Inthe illustrated embodiment, the controller (12CON) includes one or moreprocessors (12PR), a random access memory (RAM) (12RAM), a read onlymemory (ROM) (12ROM), a switching assembly (12SA), a voltage monitor(12VM), and a communication bus (12BUS). The one or more processors(12PR) is communicatively coupled with each of the RAM (12RAM), the ROM(12ROM), the switching assembly (12SA), and the voltage monitor (12VM).The switching assembly (12SA) is operatively coupled with each of thefive switches (S₁, S₂, S₃, S₄, S₅) to control switching of each of thefive switches (S₁, S₂, S₃, S₄, S₅) under the control of the one or moreprocessors (12PR). The voltage monitor (12VM) is operatively coupledwith the input terminals 26, 28 and the output terminals 30, 32. Thevoltage monitor (12VM) monitors and communicates the magnitude of eachof the low voltage-side voltage and the high voltage-side voltage to theprocessor(s) (12PR). The RAM (12RAM) stores instructions executable bythe processor(s) (12PR) to cause the processor(s) (12PR) to control thefive switches (S₁, S₂, S₃, S₄, S₅) as described below. The ROM (12RAM)stores operating system instructions executable by the processor(s)(12PR) for operation of the processor(s) (12PR). Since the DC-DCconverter 12 is bidirectional, operation of the DC-DC converter 12 isexplained for energy transfer in both the normal output and reverse (orregenerative) directions. The input- or low voltage-side source voltageis denoted by v_(L) and high voltage- or load- or output-side voltage isdenoted by V_(H).

Nomenclature: Symbols and variables used herein is set forth below:

Variables Description Variables Description v_(L) Low side voltage (V)The voltage i_(L) Current in low side branch across capacitor C_(L) (V).v_(H) High side voltage (V) i_(H) Current in high side branch Also equalto The voltage across capacitor C_(H) (V). v_(L1) The voltage acrossinductor L₁ (V). i_(L1) The current through inductor L₁ (A). v_(L2) Thevoltage across inductor L₂ (V). i_(L2) The current through inductor L₂(A). v_(C1) The voltage across capacitor C₁ i_(C1) The current throughcapacitor C₁ (A). (V). v_(C2) The voltage across capacitor C₂ (V).i_(C2) The current through capacitor C₂ (A). v_(CH) The voltage acrosscapacitor C_(H) i_(CH) The current through capacitor C_(H) (A). (V).v_(CL) The voltage across capacitor C_(L) i_(CL) The current throughcapacitor C_(L) (A). (V). v_(s1) The voltage across switch S₁ (V).i_(s1) The current through switch S₁ (A). v_(s2) The voltage acrossswitch S₂ (V). i_(s2) The current through switch S₂ (A). v_(s3) Thevoltage across switch S₃ (V). i_(s3) The current through switch S₃ (A).v_(s4) The voltage across switch S₄ (V). i_(s4) The current throughswitch S₄ (A). v_(s5) The voltage across switch S₅ (V). i_(s5) Thecurrent through switch S₅ (A). f_(sw) Switching frequency in Hz$T = \frac{1}{f_{sw}}$ Switching period in sec. T_(ON) ON period ofswitch in sec. T_(OFF) OFF period of switch in sec.$D = \frac{T_{ON}}{T_{OFF}}$ Duty cycle Note: The lower-case lettersindicate the instantaneous value a, upper case letter indicates the timeindependent value such as root mean square (RMS) value or average/DCvalue

A. Step-Up or Boost Mode of Operation (Energy Transfer from Input Sourceto Output Load)

The step-up mode of operation of the DC-DC converter 12 is illustratedin FIG. 3 . In step up mode only switch S₁ and switch S₂ are controlledand each of the other switches S₃, S₄, S₅ is maintained in an OPENstate. While each of the switches S₃, S₄, S₅ is maintained in the OPENstate, the switch body diodes 38, 40, 42 participate in the energytransfer. Let T be the switching period and the ON time T_(ON)=DT, whereD is the duty cycle given by

$D = \frac{T{on}}{T}$

and (1−D)T is OFF time. The step-up mode of operation of the DC-DCconverter 12 can be achieved by three different combinations of gatingsignals. PWM pulses of the gating signals are described herein andillustrated in FIGS. 4(a), 4(b), and 4(c.)

1. Step-Up Operation Mode PWM1

In a step-up operation mode PWM1, switch S₁ and switch S₂ are gated in acomplementary mode as illustrated in FIG. 4(a). In the step-up operationmode PWM1, switch S₁ is in a CLOSED state for DT and switch S₂ is in anOPEN state for (1−D)T. In both intervals, energy is transferred from theinput source to the inductors L₁, L₂, and from the inductors L₁, L₂ tothe output capacitor C_(H). For the step-up operation mode PM1 of theDC-DC converter 12, a plot 44 of steady state voltage gain

$G = \frac{V_{H}}{V_{L}}$

for different values of D is shown in FIG. 5 . From FIG. 5 , it can beseen that the minimum voltage gain G=5.824 for the step-up operationmode PWM1 is produced when D=0.414.

2. Step-Up Operation Mode PWM2

In a step-up operation mode PWM2, switch S₁ and switch S₂ are gated in acomplementary mode as illustrated in FIG. 4(b). In the step-up operationmode PWM2, switch S₁ is in a CLOSED state for (1−D)T and switch S₂ is inan OPEN state for (D)T. In both intervals, energy is transferred fromthe input source to the inductors L1, L2, and from the inductors L1, L2to the output capacitor C_(H). For the step-up operation mode PWM2 ofthe DC-DC converter 12, a plot 46 of steady state voltage gain

$G = \frac{V_{H}}{V_{L}}$

for different D is shown in FIG. 5 . From FIG. 5 , it can v_(L), be seenthat the minimum voltage gain G=5.824 for the step-up operation modePWM2 is produced when D=0.586.

3. Step-Up Operation Mode PWM3

In a step-up operation mode PWM3, switch S₁ and switch S₂ are gated in acomplementary mode as illustrated in FIG. 4(c). In the step-up operationmode PWM3, switch S₁ and switch S₂ have the same duty cycle variations,arranged complementary in nature. For D>0.5, there is an interval whereswitch S₁ and switch S₂ both are in the CLOSED state simultaneously andfor D<0.5, there is an interval where switch S₁ and switch S₂ both arein the OPEN state simultaneously. In the step-up operation mode PWM3,the DC-DC converter 12 behaves like a normal boost converter in forwardenergy transfer and like a normal buck converter in reverse energytransfer.

B. Step-Down Mode (Buck Mode) of Operation (Energy Transfer from OutputLoad Source to Input Load)

FIG. 6 illustrates a step-down mode (buck mode) of operation of theDC-DC converter 12. In the step-down mode of operation, the DC-DCconverter 12 transfers energy from an output-side source 48 (through theoutput terminals 30, 32) to an input-side load 50 (through the inputterminals 26, 28). In the step-down mode of operation, each of theswitch S₁ and the switch S₂ is maintained in the OPEN state and theswitches S₃, S₄ and S₅, are gated. Although each of the switch S₁ andthe switch S₂ is maintained in the open state, the switch body diodes34, 36 participate in the energy transfer depending on the voltage biasacross each of the switch body diodes 34, 36. The step-down mode ofoperation of the DC-DC converter 12 can be achieved by either of twodifferent combination of gating signals as explained below.

1) Step-Down Operation Mode PWM1

In a step-down operation mode PWM1, switch S₁ and switch S₂ are gated ina complementary mode illustrated in FIG. 7(a). In the step-downoperation mode PWM1, switch S₄ and switches S₃, S₅ are gated in acomplementary mode in which S₄ is in the CLOSED state for DT andswitches S₃, S₅ are in the CLOSED state for (1-D)T. In both theintervals, energy is transferred from the output-side source 48 (throughthe output terminals 30, 32) to the input-side load 50 (through theinput terminals 26, 28). For the step-up operation mode PWM1 of theDC-DC converter 12, a plot 52 of steady state voltage gain

$G = \frac{V_{H}}{V_{L}}$

for different D is shown in FIG. 8 . From FIG. 8 , it can be seen thatthe minimum voltage gain

$G = {\frac{1}{5.824} = 0.172}$

for the DC-DC converter 12 in the set-down operation mode PMW 1 isproduced when D=0.414.

2) Step-Down Operation Mode PWM2

In a step-down operation mode PWM2, switch S₁ and switch S₂ are gated ina complementary mode illustrated in FIG. 7(b). In the step-downoperation mode PWM1, switch S₄ and switches S₃, S₅ are gated in acomplementary mode in which switch S₄ is in the CLOSED state for (1−D) Tand switches S₃, S₅ are in the CLOSED state for DT. In both intervals,energy is transferred from the output-side source 48 to the input-sideload 50. For the step-down operation mode PWM2, a plot 54 of steadystate voltage gain

$G = \frac{V_{H}}{V_{L}}$

for different D is shown in FIG. 8 . From FIG. 8 , it can be seen thatthe minimum voltage gain

$G = {\frac{1}{5.824} = 0.172}$

for the step-down operation mode PWM2 is produced when D=0.414.

Steady State Analysis and Simulation Results

Steady state analysis and simulation was performed for the DC-DCconverter 12 for each of the step-up operation mode PWM1, the step-upoperation mode PWM2, the step-down operation mode PWM1, and thestep-down operation mode PWM2. The circuit parameters used in thesimulation are listed in Table I below.

TABLE 1 Circuit Parameters For Simulation Parameter Value ParameterValue V_(L)  48 V R_(H), R_(L) 300 Ω, 7.68 Ω V_(H) 300 V L₁, r_(L1) 170μH, 27 mΩ P 300 W L₂, r_(L2) 340 μH, 50 mΩ ƒ_(sw) 100 kHz C₁, r_(C1)  47μF, 20 mΩ C_(L) 220 μF C₂, r_(C2)  47 μF, 20 mΩ r_(CL)  20 mΩ C_(H),r_(CH)  47 μF, 20 mΩ

Step-Up Operation Mode PWM1

In the step-up operation mode PWM1, switch S₁ is in the CLOSED state andswitch S₂ is in the OPEN state for DT duration, and switch S₂ is in theCLOSED state and switch S₁ is in the OPEN state for (1−D)T duration.Switches S₃, S₄ and S₅ maintained in the OPEN state as shown in FIG. 5 .

A. Steady Sate Analysis for 0≤t<DT Interval

The circuit status for the DC-DC converter 12 in the step-up operationmode PWM1 in the 0≤t<DT interval is illustrated in FIG. 9(a) and anequivalent circuit for the DC-DC converter 12 in the step-up operationmode PWM1 in the 0≤t<DT interval is shown in FIG. 9(b). The inductorvoltages and capacitor current expressions are written as follows:

v _(L1) =v _(L)  (1);

v _(L2) =v _(L) −v _(C1) +v _(C2)  (2);

i _(C1) =i _(L2)  (3);

i _(C2) =−i _(L2)  (4); and

i _(CH) =−i _(H)  (5).

B. Steady Sate Analysis for DT≤t≤(1−D)T Interval

The circuit status for the DC-DC converter 12 in the step-up operationmode PWM1 in the DT≤t≤(1−D)T interval is illustrated in FIG. 10(a) andan equivalent circuit for the DC-DC converter 12 in the step-upoperation mode PWM1 in the DT≤t≤(1−D)T interval is shown in FIG. 10(b).The inductor voltages and capacitor current expressions are written asfollows:

v _(L1) =v _(L) −v _(C2)  (6);

v _(L2) =v _(L)  (7);

i _(C1) =i _(C2) −i _(L1)  (8);

i _(C2) =i _(L1) +i _(C1)  (9); and

i _(CH) =i _(C1) −iH  (10).

In steady state, the capacitor average current and inductor averagevoltage over one switching interval should be zero. By applyingvolt-seconds balance principle to the L₁ and L₂ over one switchinginterval, we get following voltage relations:

$\begin{matrix}{{\begin{matrix}{{V_{C1} = \frac{V_{L}}{D\left( {1 - D} \right)}},} & {V_{C2} =}\end{matrix}\frac{V_{L}}{\left( {1 - D} \right)}},} & (11)\end{matrix}$${{and}V_{H}} = {{V_{C1} + V_{C2}} = \frac{\left( {1 + D} \right)V_{L}}{D\left( {1 - D} \right)}}$

By implementing charge-seconds balance principle to the all thecapacitors over one switching instant, we get following currentrelations:

$\begin{matrix}{\begin{matrix}{{I_{L1} = \frac{2I_{H}}{\left( {1 - D} \right)}},} & {I_{L2} = \frac{I_{H}}{D}}\end{matrix},{{{and}I_{H}} = \frac{{D\left( {1 - D} \right)}I_{L}}{\left( {1 + D} \right)}}} & (12)\end{matrix}$

C. Switch Voltage and Current Stress

The following gives the maximum voltage stress across each switch andmaximum current through switches. This is helpful in selecting voltageand current rating of the switches.

$\begin{matrix}\left. \begin{matrix}{V_{S1} = V_{C2}} \\{V_{S2} = {V_{C1} - V_{C2}}} \\{V_{S3} = V_{C1}} \\{V_{S4} = V_{C1}} \\{V_{S5} = V_{C2}}\end{matrix} \right\} & (13)\end{matrix}$ $\begin{matrix}\left. \begin{matrix}{I_{S1} = I_{L}} \\{I_{S2} = \frac{{D\left( {1 - D} \right)}I_{H}}{D\left( {1 - D} \right)}} \\{I_{S3} = \frac{I_{H}}{\left( {1 - D} \right)}} \\{I_{S4} = \frac{I_{H}}{D}} \\{I_{S5} = \frac{I_{H}}{\left( {1 - D} \right)}}\end{matrix} \right\} & (14)\end{matrix}$

D. Simulation Verifications

The DC-DC converter 12 is simulated for circuit condition given in TableI for D=0.55 and (1-D)=0.45. FIG. 11(a) shows the gate pulses G_(s1),G_(s2), G_(s3), G_(s4), and G_(s5) for switches S₁, S₂, S₃, S₄ and S₅respectively. Voltages across each of the inductors L₁, L₂ andcapacitors C₁, C₂ as well as low voltage and high voltage are shown inFIG. 11(b). In FIG. 11 (c), the voltages across the switches areexpresses as V_(S1), V_(S2), V_(S3), V_(S4) and V_(S5) respectively. Theinput current IL, current through the L₁ and L₂ are as I_(L1) and I_(L2)respectively are shown in FIG. 11(d). Current through each of theswitches are shown in FIG. 11(e).

The inductors L₁, L₂ are designed to limit the current ripple to lessthan 35% which is clear from the simulation results. One advantage ofthe step-up operation mode PWM1 control strategy is that the inputripple current will be less than (35/2) % because the operation ofcharging and discharging the inductors (L₁ and L₂) is complementary innature. Moreover, the total current is the summation of the bothinductor’ currents (I_(L1) and I_(L2)), significantly reducing thesource current ripple.

The simulation results show the for 48 V input voltage (V_(L)), theoutput voltage (V_(H)) is 300 V when operating at 0.55 duty cycle. Inone example, the DC-DC converter 12 operating at 300 W provides for anoutput current rating (I_(H)) obtained as 1 A, with capacitor voltagesbeing V_(c1)=200 V and V_(c2)=100 V.

Step-Up Operation Mode PWM2

The operation of the DC-DC converter 12 in the step-up operation modePWM2 is similar to the operation in the step-up operation mode PWM1except that the CLOSED state and OPEN state interval of the switch S₁and the switch S₂ are interchanged. So, FIG. 9 is also applicable forthe step-up operation mode PWM2.

A. Steady Sate Analysis for 0≤t<DT Interval

The circuit status is given in FIG. 9(a) and equivalent circuit is shownin FIG. 9(b). Applying KCL and KVL in FIG. 9(b), the inductor voltagesand capacitors current expression are written as follows,

v _(L1) =v _(L) −v _(C2)  (15)

v _(L2) =v _(L)  (16)

i _(C1) =i _(C2) −i _(L1)  (17)

i _(C2) =i _(L1) +i _(C1)  (18)

i _(CH) =−i _(C1) −i _(H)  (19)

B. Steady Sate Analysis for DT≤t≤(1−D)T Interval

The circuit in interval DT≤t≤(1−D)T is shown in FIG. 10(a) and theequivalent circuit is shown in FIG. 10(b) for the step-up operation modePWM2. The inductor voltages and capacitors current expression arewritten as follows,

v _(L1) =v _(L)  (20)

v _(L2) =v _(L) −v _(C1) +v _(C2)  (21)

i _(C1) =i _(L2)  (22)

i _(C2) =−i _(L2)  (23)

i _(CH) =−i _(H)  (24)

In steady state, the capacitor average current and inductor averagevoltage over one switching interval should be zero. So, by utilizingvolt-seconds balance principle to the L₁ and L₂ over one switchinginterval, we get following voltage relations:

$\begin{matrix}{{\begin{matrix}{{V_{C1} = \frac{V_{L}}{D\left( {1 - D} \right)}},} & {V_{C2} =}\end{matrix}\frac{V_{L}}{D}},{V_{H} = {{V_{C1} + V_{C2}} = \frac{\left( {2 - D} \right)V_{L}}{D\left( {1 - D} \right)}}}} & (25)\end{matrix}$

The currents are given by:

$\begin{matrix}{\begin{matrix}{{I_{L1} = \frac{2I_{H}}{D}},} & {{I_{L2} = \frac{I_{H}}{\left( {1 - D} \right)}},{{{and}I_{H}} =}}\end{matrix}\frac{{D\left( {1 - D} \right)}I_{L}}{\left( {2 - D} \right)}} & (26)\end{matrix}$

C. Switch Voltage and Current Stress

The following gives the maximum voltage stress across each switch andmaximum current through switches. This is helpful in selecting voltageand current rating of the switches.

$\begin{matrix}\left. \begin{matrix}{V_{S1} = \frac{V_{L}}{D}} \\{V_{S2} = {V_{C1} - V_{C2}}} \\{V_{S3} = \frac{V_{L}}{D\left( {1 - D} \right)}} \\{V_{S4} = \frac{V_{L}}{D\left( {1 - D} \right)}} \\{V_{S5} = \frac{V_{L}}{D}}\end{matrix} \right\} & (27)\end{matrix}$ $\begin{matrix}\left. \begin{matrix}{I_{S1} = I_{L}} \\{I_{S2} = \frac{\left( {2 - D} \right)I_{H}}{D\left( {1 - D} \right)}} \\{I_{S3} = \frac{I_{H}}{\left( {1 - D} \right)}} \\{I_{S4} = \frac{I_{H}}{\left( {1 - D} \right)}} \\{I_{S5} = \frac{I_{H}}{D}}\end{matrix} \right\} & (28)\end{matrix}$

D. Simulation Verifications

The simulation conditions as shown in Table I are used. The nominal dutycycle is D=0.45. So, the switch S₂ is operated as 0.45 duty cycle andswitch S₁ operated at 0.55 duty cycle as shown in FIG. 12 . Thesimulation results show the for 48 V input voltage (V_(L)), the outputvoltage (V_(H)) is 300 V when operating at 0.45 duty cycle. For a designthat takes 300 W, the output current rating (I_(H)) is obtained as 1 A,the input current (I_(H)) is 6.25 A, inductor currents I_(L1)=4.43 A andI_(L2)=1.82 A, and capacitor voltages are V_(C1)=194 V and V_(C2)=106 V.Detailed results are given in the FIG. 12 .

Step-Down Operation Mode PWM1

In step-down mode of operation PWM1, the load and source terminal areinterchanged and energy flow is high side to low side. In the DTinterval, only switch S₄ is in the CLOSED state and switches S₃, S₅ arein the OPEN state. In the (1-D)T interval, switches S₃, S₅ are in theCLOSED state and switch S₄ is in the OPEN state. Switches S₁, S₂ aremaintained in the OPEN state in the step-down mode of operation PWM1 asdescribed herein. The circuit condition for step-down mode of operationis shown in FIG. 6 .

A. Steady Sate Analysis for 0≤t<DT Interval

The circuit status is given in FIG. 13(a) and equivalent circuit isshown in FIG. 13(b). By applying the KVL and KCL in the equivalentcircuit, the inductor voltages and capacitors current expression arewritten as follows:

v _(L1) =−v _(L)  (29);

v _(L2) =−v _(L) +v _(C1) −v _(C2)  (30);

i _(C1) =−i _(L2)  (31);

i _(C2) =i _(L2)  (32); and

i _(CH) =i _(H)  (33).

B. Steady Sate Analysis for DT≤t≤(1−D)T Interval

The circuit in interval DT≤t≤(1−D)T is showing in FIG. 14(a) andequivalent circuit is shown in FIG. 14(b) for the step-down operationmode PWM1. The inductor voltages and capacitors current expression arewritten as follows:

v _(L1) =−v _(L) +v _(C2)  (34);

v _(L2) =−v _(L)  (35);

i _(C1) =i _(C2) +i _(L1)  (36);

i _(C2) =−i _(L1) +i _(C1)  (37);

i _(CH) =−i _(C1) +i _(H)  (38); and

i _(CL) =i _(L1) +i _(L2) −i _(L)  (39).

In steady state, the capacitor average current and inductor averagevoltage over one switching interval should be zero. By utilizingvolt-seconds balance principle to the L₁ and L₂ over one switchinginterval, we get following voltage relations:

$\begin{matrix}{{V_{C1} = \frac{V_{H}}{\left( {1 + D} \right)}},{V_{C2} = \frac{{DV}_{H}}{\left( {1 + D} \right)}},{V_{L} = \frac{{D\left( {1 - D} \right)}V_{H}}{\left( {1 + D} \right)}}} & (40)\end{matrix}$

By implementing charge-seconds balance principle to the all thecapacitors over one switching instant, we get following currentrelations:

$\begin{matrix}{{I_{L2} = \frac{\left( {1 + D} \right)I_{H}}{\left( {1 - D} \right)}},{I_{L2} = \frac{\left( {1 + D} \right)I_{H}}{D}},{{{and}{}I_{H}} = \frac{{D\left( {1 + D} \right)}I_{L}}{\left( {1 + D} \right)}}} & (41)\end{matrix}$

C. Switch Voltage and Current Stress

The maximum voltage and current rating of the switches are as follows:

$\begin{matrix}\left. \begin{matrix}{V_{S1} = \frac{DV_{H}}{\left( {1 + D} \right)}} \\{V_{S2} = {V_{C1} - V_{C2}}} \\{V_{S3} = \frac{V_{H}}{\left( {1 + D} \right)}} \\{V_{S4} = \frac{V_{H}}{\left( {1 + D} \right)}} \\{V_{S5} = {\frac{V_{H}}{\left( {1 + D} \right)} - V_{H}}}\end{matrix} \right\} & (42)\end{matrix}$ $\begin{matrix}\left. \begin{matrix}{I_{S1} = I_{L}} \\{I_{S2} = \frac{\left( {1 + D} \right)I_{H}}{D\left( {1 - D} \right)}} \\{I_{S3} = \frac{I_{H}}{\left( {1 - D} \right)}} \\{I_{S4} = \frac{\left( {1 + D} \right)I_{H}}{D}} \\{I_{S5} = \frac{I_{H}}{\left( {1 - D} \right)}}\end{matrix} \right\} & (43)\end{matrix}$

D. Simulation Verifications

In the step-down operation mode PWM1 control strategy, the maximumvoltage buck ration is G=0.172 at the duty cycle of D=0.414. The circuitparameters are given in Table I and same as that of Boost operationexcept the input and output terminals are interchanged.

The energy transfer is from V_(H) to V_(L) side. The nominal duty cycleis 0.445. The switch S₄ is on for 0.45 T interval and switches S₃ and S₅are ON for (1−D)T=0.55 T duty cycle as shown in FIG. 15 . No PWM signalis applied for switches S₁, and S₂. The converter is bi-directional, theripple voltage and current ripple in capacitors and inductors is same asthat of boost mode operation, which is also clear from the FIG. 15 . Theoutput current rating (I_(L)) is 6.25 A. The capacitor voltages areV_(c1)=194V, V_(C2)=106V and V_(CH)=V_(H)=300V. The waveforms are givenin the FIG. 15 .

Step-Down Operation Mode PWM2

The operation of the DC-DC converter 12 is similar to the step-downoperation mode PWM2 except that the ON and OFF interval of the switch S₄is interchanged with the switches S₃, S₅. So, the circuit given in FIG.13 and FIG. 14 are also applicable for the step-down operation modePWM2.

A. Steady Sate Analysis for 0≤t<DT Interval

The interval DT is showing in FIG. 13(b) for the step-down operationmode PWM2. The inductor voltages and capacitors current expression arewritten as follows:

v _(L1) =−v _(L) +v _(C2)  (44);

v _(L2) =−v _(L)  (45);

i _(C1) =i _(C2) +i _(L1)  (46);

i _(C2) =−i _(L1) +i _(C1)  (47); and

i _(CH) =−i _(C1) +i _(H)  (48).

B. Steady Sate Analysis for DT≤t≤(1−D)T Interval

For the step-down operation mode PWM2, the DC-DC converter 12 ininterval (1-D)Tis shown in FIG. 14(b). The inductor voltages andcapacitors current expression are written as follows:

v _(L1) =−v _(L)  (49);

v _(L2) =−v _(L) +v _(C1) −v _(C2)  (50);

i _(C1) =−i _(L2)  (51);

i _(C2) =i _(L2)  (52); and

i _(CH) =i _(H)  (53).

In steady state, the capacitor average current and inductor averagevoltage over one switching interval should be zero. So, by utilizingvolt-seconds balance principle to the L₁ and L₂ over one switchinginterval, we get following voltage relations:

$\begin{matrix}{{V_{C1} = \frac{V_{H}}{\left( {2 - D} \right)}},{V_{C2} = \frac{\left( {1 - D} \right)V_{H}}{\left( {2 - D} \right)}},{V_{L} = \frac{{D\left( {1 - D} \right)}V_{H}}{\left( {2 - D} \right)}}} & (54)\end{matrix}$

By implementing charge-seconds balance principle to the all thecapacitors over one switching instant, we get following currentrelations:

$\begin{matrix}{{I_{L1} = \frac{\left( {2 - D} \right)I_{H}}{D}},{I_{L2} = \frac{\left( {2 - D} \right)I_{H}}{\left( {1 - D} \right)}},{{{and}{}I_{L}} = \frac{\left( {2 - D} \right)I_{L}}{D\left( {1 - D} \right)}}} & (55)\end{matrix}$

C. Switch Voltage and Current Stress

The maximum voltage and current stress of the switches are as follows.

$\begin{matrix}\left. \begin{matrix}{V_{S1} = \frac{\left( {1 - D} \right)V_{H}}{\left( {2 - D} \right)}} \\{V_{S2} = {V_{C1} - V_{C2}}} \\{V_{S3} = \frac{V_{H}}{\left( {2 - D} \right)}} \\{V_{S4} = \frac{V_{H}}{\left( {2 - D} \right)}} \\{V_{S5} = {\frac{V_{H}}{\left( {2 - D} \right)} - V_{H}}}\end{matrix} \right\} & (56)\end{matrix}$ $\begin{matrix}\left. \begin{matrix}{I_{S1} = I_{L}} \\{I_{S2} = \frac{\left( {2 - D} \right)I_{L}}{D\left( {1 - D} \right)}} \\{I_{S3} = \frac{I_{H}}{D}} \\{I_{S4} = \frac{\left( {2 - D} \right)I_{H}}{\left( {1 - D} \right)}} \\{I_{S5} = \frac{I_{H}}{D}}\end{matrix} \right\} & (57)\end{matrix}$

D. Simulation Verifications

In the step-down operation mode PWM2, the maximum buck gain is G=0.172at the duty cycle of D=0.586. Nominal duty cycle is 0.54806. So, theswitch S₃, S₅ is operated as 0.45194 duty cycle and switch S₄ operatedat 0.54806 duty cycle as shown in FIG. 16 .

The simulation results show the for 300 V input voltage (V_(H)), theoutput voltage (V_(L)) is 48V when operating at 0.54806 duty cycle. Theprototype is design for 300 W so the output current rating (I_(L)) isobtained as 6.25 A. The capacitor voltages are V_(c1)=194V andV_(c2)=106V. Other parameters are given in the FIG. 16 .

Design Criteria and Selection of Components

In order to ensure the operation of the DC-DC converter 12 in continuousconduction mode (CCM), it is important to select the values of inductorsand capacitors so that the current ripple in inductors and the voltageripple in the capacitors are within the desired value. Operating theconverter below this rating leads to the converter in discontinuousconduction mode (DCM). The selection of voltage and current rating ofswitches are based on the peak reverse voltage across the switches aswell as peak current through the switches.

The capacitors and inductors are designed to limit the ripple voltageand switching frequency current ripple. Thus, for the proposedconverter, the inductors and capacitors are obtained as follows:

$\begin{matrix}{L_{i} = \frac{{DV}_{Li}}{\Delta i_{Li}f_{s}}} & (58)\end{matrix}$ $\begin{matrix}{C_{i} = \frac{DI_{ci}}{\Delta V_{ci}f_{s}}} & (59)\end{matrix}$

where i=1 and 2, Δi_(L1) and Δi_(L2) represent ripple currents in L₁ andL₂. ΔV_(c1) and ΔV_(c2) represent ripple voltages in C₁ and C₂. f_(s) isthe switching frequency. The design procedures for all the PWMstrategies are same.

The above quantities for PWM1 can be derived in terms of V_(L) and I_(H)as follows. As the proposed converter is bi-directional the designpercentage ripple will be same for boost mode of operation as well asbuck mode of operations.

$\begin{matrix}{L_{1} = \frac{{D\left( {1 - D} \right)}V_{L}}{2\Delta i_{H}f_{s}}} & (60)\end{matrix}$ $\begin{matrix}{L_{2} = \frac{{D\left( {1 - D} \right)}V_{L}}{\Delta i_{LH}f_{s}}} & (61)\end{matrix}$ $\begin{matrix}{C_{1} = \frac{{D\left( {1 - D} \right)}I_{H}}{\Delta v_{L1}f_{s}}} & (62)\end{matrix}$ $\begin{matrix}{C_{2} = \frac{\left( {1 - D} \right)I_{H}}{\Delta v_{L}f_{s}}} & (63)\end{matrix}$ $\begin{matrix}{C_{H} = \frac{{D^{2}\left( {1 - D} \right)}I_{H}}{\Delta v_{cL}{f_{s}\left( {1 - D} \right)}}} & (64)\end{matrix}$

where Δi_(H), is the current ripple of the I_(H) and Δv_(CL) is thevoltage ripple of the V_(L).

For buck mode, C_(L) is the filter capacitor across the load or outputterminals and is given by

$\begin{matrix}{C_{L} = \frac{\left( {1 - D} \right)I_{H}}{\Delta v_{L}f_{s}{D\left( {1 - D} \right)}}} & (65)\end{matrix}$

Where Δv_(C) is the voltage ripple across C_(L).

For the converter to operate in continuous conduction mode (CCM) thecritical values of the inductors are

$\begin{matrix}{L_{1{CR}} = \frac{{D\left( {1 - D} \right)}V_{L}}{4\Delta i_{H}f_{s}}} & (66)\end{matrix}$ $\begin{matrix}{L_{2{CR}} = \frac{{D\left( {1 - D} \right)}V_{L}}{2\Delta i_{H}f_{s}I}} & (67)\end{matrix}$

Small Signal Analysis of the Proposed Converter

The control to output transfer function for both mode (i.e. Boost modeof operation and Buck mode of operation) are presented in this section.The dynamic performance is very similar in PWM1 and PWM2, so the smallsignal analysis of only PWM1 strategy is presented.

A. Small Signal Analysis for Boost Mode of Operation

The simplified equivalent circuit of proposed converter is shown in FIG.4 . Let rL1, rL2 are the parasitic DC resistances of the inductors L1and L2. Let r_(C1), r_(C2), r_(CH) are the ESR of the capacitances C1,C2 and CH respectively.

After applying perturbation and linearization technique to equationsleads to following state space model.

K{dot over ({circumflex over (x)})}=A{circumflex over (x)}+B{circumflexover (v)} _(L)+[(A ₁ −A ₂)X+(B ₁ −B ₂)V _(L)]{circumflex over (d)}  (68)

{dot over ({circumflex over (x)})}=(K ⁻¹ A){circumflex over (x)}+(K ⁻¹B){circumflex over (v)} _(L) +K ⁻¹[(A ₁ −A ₂)X+(B ₁ −B ₂)V_(L)]{circumflex over (d)}  (69)

Let. S₁=(K⁻¹ A);

-   -   S₂=(K⁻¹B);    -   S₃=K⁻¹ [(A₁−A₂)X+(B₁−B₂)V_(L)]

After simplification,

{dot over ({circumflex over (x)})}=S ₁ {circumflex over (x)}+S ₂{circumflex over (v)} _(L) +S ₃ {circumflex over (d)}

A=A ₁ D+A ₂(1−D), and B=B ₁ D+B ₂(1−D)

From (68), the control to output transfer function for the proposedconverter deduced as follows:

$\begin{matrix}{\frac{{\hat{v}}_{H}}{\partial} = {{\begin{bmatrix}0 & 0 & 0 & 0 & 1\end{bmatrix}\left\lbrack {{SI} - S_{1}} \right\rbrack}^{- 1}S_{3}}} & (70)\end{matrix}$

Therefore, the boost mode of operation in the ON interval can be writtenas:

$\begin{matrix}{{K\overset{.}{X}} = {{A_{1}X} + {B_{1}V_{L}}}} & (71)\end{matrix}$ $K = \begin{bmatrix}L_{1} & 0 & 0 & 0 & 0 \\0 & L_{2} & 0 & 0 & 0 \\0 & 0 & C_{1} & 0 & 0 \\0 & 0 & 0 & C_{2} & 0 \\0 & 0 & 0 & 0 & C_{H}\end{bmatrix}$ $\begin{matrix}{A_{1} = \begin{bmatrix}R_{L_{1}} & 0 & 0 & 0 & 0 \\0 & L_{2} & 0 & 0 & 0 \\0 & 0 & C_{1} & 0 & 0 \\0 & 0 & 0 & C_{2} & 0 \\0 & 0 & 0 & 0 & C_{H}\end{bmatrix}} & (72)\end{matrix}$ $\begin{matrix}{B_{1}^{T} = \begin{bmatrix}1 & 1 & 0 & 0 & 0\end{bmatrix}} & (73)\end{matrix}$

Where r_(C)=r_(C1)+r_(C2)

In the OFF interval:

$\begin{matrix}{{K\overset{.}{X}} = {{A_{1}X} + {B_{1}V_{L}}}} & (73)\end{matrix}$ $\begin{matrix}{A_{2} = \begin{bmatrix}{- \left( {r_{L1} + \frac{r_{c1}r_{c2}}{r_{c}}} \right)} & 0 & \frac{r_{c2}}{r_{c}} & {- \frac{r_{c1}}{r_{c}}} & {- \frac{r_{c2}}{r_{c}}} \\0 & {- r_{L2}} & 0 & 0 & 0 \\{- \frac{r_{c2}}{r_{c}}} & 0 & {- \frac{1}{r_{c}}} & {- \frac{1}{r_{c}}} & \frac{1}{r_{c}} \\\frac{r_{c1}}{r_{c}} & 0 & {- \frac{1}{r_{c}}} & {- \frac{1}{r_{c}}} & \frac{1}{r_{c}} \\\frac{r_{c2}}{r_{c}} & 0 & \frac{1}{r_{c}} & \frac{1}{r_{c}} & {- \left( {\frac{1}{r_{c}} + \frac{1}{r_{H}}} \right)}\end{bmatrix}} & (74)\end{matrix}$ $\begin{matrix}{B_{1}^{T} = \begin{bmatrix}1 & 1 & 0 & 0 & 0\end{bmatrix}} & (75)\end{matrix}$

The representation (˜) denotes the small signal ac variation of thesignal. The lower cases correspond to the instantaneous values, andupper cases correspond to the steady state values.

X ^(T)=[i _(L1) i _(L2) v _(C1) v _(C2) v _(H)]

By using equation (69) and using the parameters used in the proposedconverter (Table I), the control to output transfer function can bewritten as:

d ^ = - 1.9 * 10 5 ⁢ S 4 - 7.37 * 10 10 ⁢ S 3 + 8.33 * 10 15 ⁢ S 2 - 2.34 *10 17 ⁢ S + 2.42 * 10 23 4 ⁢ S 5 + 2.9 * 10 10 ⁢ S 4 + 1.5 * 10 9 ⁢ S 3 +1.58 * 10 14 ⁢ S 2 + 3.85 * 10 16 ⁢ S + 4.68 * 10 20 ( 76 ) d ^ = - 1.19 *10 5 ⁢ S 4 - 4.97 * 10 10 ⁢ S 3 + 3.61 * 10 15 ⁢ S 2 - 6.02 * 10 17 ⁢ S +8.95 * 10 22 2.52 S 5 + 1.82 * 10 6 ⁢ S 4 + 9.5 * 10 8 ⁢ S 3 + 9.93 * 1013 ⁢ S 2 + 2.41 * 10 16 ⁢ S + 2.92 * 10 20

B. Small Signal Analysis for Buck Mode of Operation

For the buck mode of operations of PWM1, the matrixes are written as:

In the ON interval:

$\begin{matrix}{{K\overset{.}{X}} = {{A_{1}X} + {B_{1}V_{H}}}} & (77)\end{matrix}$ $K = \begin{bmatrix}L_{1} & 0 & 0 & 0 & 0 \\0 & L_{2} & 0 & 0 & 0 \\0 & 0 & C_{1} & 0 & 0 \\0 & 0 & 0 & C_{2} & 0 \\0 & 0 & 0 & 0 & C_{H}\end{bmatrix}$ $\begin{matrix}{A_{1} = \begin{bmatrix}{- r_{L1}} & 0 & 0 & 0 & {- 1} \\0 & {- \left( {r_{L2} + r_{c}} \right)} & 1 & {- 1} & {- 1} \\0 & {- 1} & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 \\1 & 1 & 0 & 0 & {- \frac{1}{R_{L}}}\end{bmatrix}} & (78)\end{matrix}$ $\begin{matrix}{B_{1}^{T} = \left\lbrack \begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}0 & 0\end{matrix} & 0\end{matrix} & 0\end{matrix} & \left. 0 \right\rbrack\end{matrix} \right.} & (79)\end{matrix}$

Where r_(C)=r_(C1)+r_(C2)

In the OFF interval:

$\begin{matrix}{{K\overset{.}{X}} = {{A_{2}X} + {B_{2}V_{H}}}} & (80)\end{matrix}$ $A_{2} = \begin{bmatrix}{- \left( {r_{L1} + \frac{r_{c1}r_{c2}}{r_{c}}} \right)} & 0 & {- \frac{r_{c2}}{r_{c}}} & \frac{r_{c1}}{r_{c}} & {- 1} \\0 & {- r_{L2}} & 0 & 0 & {- 1} \\\frac{r_{c2}}{r_{c}} & 0 & {- \frac{1}{r_{c}}} & {- \frac{1}{r_{c}}} & 0 \\{- \frac{r_{c1}}{r_{c}}} & 0 & {- \frac{1}{r_{c}}} & {- \frac{1}{r_{c}}} & 0 \\1 & 1 & 0 & 0 & {- \frac{1}{r_{L}}}\end{bmatrix}$ $\begin{matrix}\left. {B_{2}^{T} = \begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}\left\lbrack \frac{r_{C2}}{r_{c}} \right. & 0\end{matrix} & \frac{1}{r_{c}}\end{matrix} & \frac{1}{r_{c}}\end{matrix} & 0\end{matrix}} \right\rbrack & (81)\end{matrix}$

The representation (˜) denotes the small signal ac variation of thesignal. The lower cases correspond to the instantaneous values, andupper cases correspond to the steady state values.

X ^(T)=[i _(L1) i _(L2) v _(C1) v _(C2) v _(H)]

By using equation (70) and using the parameters used in the proposedconverter (Table I), the control to output transfer function can bewritten as:

d ^ = 1.2 ⋆ 10 10 ⁢ S 2 + 8 ⋆ 10 11 ⁢ S + 5.76 ⋆ 10 17 7.24 S 4 + 7.12 ⋆10 3 ⁢ S 3 + 6.54 ⋆ 10 8 ⁢ S 2 + 3.43 ⋆ 10 11 ⁢ S + 1.45 ⋆ 10 16 ( 82 )

Non-Ideal or Practical Voltage Gain of the Proposed Converter

This section gives the effect of parasitic element such as inductors andcapacitors on voltage gain performance with duty cycle.

A. Boost Mode:

The actual practical steady state gain (G_(Practical)) for PWM1strategies is given by,

$\begin{matrix}{G_{Practical} = {\frac{V_{H}}{V_{L}} = {\frac{1 + D}{D\left( {1 - D} \right)} \star \frac{1}{1 + {\frac{2}{\left( {1 - D} \right)} \star \frac{\left( {r_{c}^{2} - r_{c2}^{2}} \right)}{r_{c2}R_{H}}} + {\frac{2D}{\left( {1 - d} \right)^{2}} \star \frac{r_{c}r_{L1}}{r_{c2}R_{H}}}}}}} & (83)\end{matrix}$

Let,

${\frac{r_{c}^{2} - r_{c2}^{2}}{r_{c2}R_{H}} = {{\frac{R_{x}}{R_{H}}{And}\frac{r_{c}r_{L1}}{r_{c2}R_{H}}} = \frac{R_{y}}{R_{H}}}},$

The above can be written as,

$\begin{matrix}{G_{Practical} = {\frac{V_{H}}{V_{L}} = {\frac{1 + D}{D\left( {1 - D} \right)} \star \frac{1}{1 + {\frac{2}{\left( {1 - D} \right)} \star \frac{R_{x}}{R_{H}}} + {\frac{2D}{\left( {1 - d} \right)^{2}} \star \frac{R_{y}}{R_{H}}}}}}} & (84)\end{matrix}$

The actual practical steady state gain (G_(Practical)) for PWM2strategies is given by,

$\begin{matrix}{G_{Practical} = {\frac{V_{H}}{V_{L}} = {\frac{2 - D}{D\left( {1 - D} \right)} \star \frac{1}{1 + {\frac{2}{D} \star \frac{r_{c}}{r_{c2}R_{H}} \star \left( {r_{c} - \frac{r_{c2}^{2}}{r_{c}} - r_{L1}} \right)} + {\frac{2}{D^{2}} \star \frac{r_{c}r_{L1}}{r_{c2}R_{H}}}}}}} & (85)\end{matrix}$

Let,

${{\frac{r_{c}}{r_{c2}R_{H}} \star \left( {r_{c} - \frac{r_{c2}^{2}}{r_{c}} - r_{L1}} \right)} = {{\frac{R_{x}}{R_{H}}{And}\frac{r_{c}r_{L1}}{r_{c2}R_{H}}} = \frac{R_{y}}{R_{H}}}},$

The above can be written as,

$\begin{matrix}{G_{Practical} = {\frac{V_{H}}{V_{L}} = {\frac{2 - D}{D\left( {1 - D} \right)} \star \frac{1}{1 + {\frac{2}{D} \star \frac{R_{x}}{R_{H}}} + {\frac{2}{D^{2}} \star \frac{R_{y}}{R_{H}}}}}}} & (86)\end{matrix}$

The influence of parasitic components on the converter gain in boostmode is very small in the interval D=0.1 to 0.9, as shown in FIG. 17with reference to PMW 1. However, the boost gain will reduce high valuesof D in the range 0.9 to 1, which is not the normal operating point ofthe converter. Similar performance can be seen for PWM2 as shown in FIG.18 .

B. Buck Mode:

The performance of voltage buck with duty cycle is also investigated insimilar manner. The non-ideal voltage transfer ration is given for PWM1as (87).

$\begin{matrix}{G_{Practical} = {\frac{V_{L}}{V_{H}} = {\frac{D\left( {1 - D} \right)}{1 + D} \star \frac{1}{1 + \frac{\left( {1 - D} \right)r_{L2}}{R_{L}} + \frac{{D\left( {1 - D} \right)}r_{c}}{R_{L}}}}}} & (87)\end{matrix}$

Let,

$\frac{r_{L2}}{R_{L}} = {{\frac{R_{x}}{R_{L}}{and}\frac{r_{c2}}{R_{L}}} = \frac{R_{y}}{R_{L}}}$

The above can be written as,

$\begin{matrix}{G_{Practical} = {\frac{V_{L}}{V_{H}} = {\frac{D\left( {1 - D} \right)}{1 + D} \star \frac{1}{1 + \frac{\left( {1 - D} \right)R_{x}}{R_{L}} + \frac{{D\left( {1 - D} \right)}R_{y}}{R_{L}}}}}} & (88)\end{matrix}$

The parasitic elements will reduce the buck gain of the duty cycle asshown in FIG. 19 . The non-ideal voltage transfer ration is given forPWM2 can be written as (89).

$\begin{matrix}{G_{Practical} = {\frac{V_{L}}{V_{H}} = {\frac{D\left( {1 - D} \right)}{2 - D} \star \frac{1}{1 + \frac{{Dr}_{L2}}{R_{L}} + \frac{{D\left( {1 - D} \right)}r_{c}}{R_{L}}}}}} & (89)\end{matrix}$

Let

$\frac{r_{L2}}{R_{L}} = {{\frac{R_{x}}{R_{L}}{and}\frac{r_{c2}}{R_{L}}} = \frac{R_{y}}{R_{L}}}$

The above can be written as,

$\begin{matrix}{G_{Practical} = {\frac{V_{L}}{V_{H}} = {\frac{D\left( {1 - D} \right)}{2 - D} \star \frac{1}{1 + \frac{{DR}_{x}}{R_{L}} + \frac{{D\left( {1 - D} \right)}R_{y}}{R_{L}}}}}} & (90)\end{matrix}$

Similar performance can be seen for PWM2 as shown in FIG. 20 .

Thus, the non-ideal performances show that the passive componentsparasitic are not dominating much as compared to the conventionalconverters. In buck mode, the desired voltage gain can be achieved inpractical system and is very close to the ideal gain.

Variations on the converter designs described above can be used asunidirectional high gain DC to DC boost converters or buck converters,as shown in FIGS. 21 and 22 .

FIG. 21 diagrammatically shows an example of a unidirectional high gainDC to DC boost converter, in accordance with various embodiments. Theunidirectional high gain DC to DC boost converter can be derived fromthe above converter shown in FIG. 2 by replacing switches S3, S4 and S5with diodes. The design details, analysis, and the dynamic model of theconverter given above for boost mode operation are valid for such theunidirectional high gain DC to DC converter.

FIG. 22 diagrammatically shows an example of a unidirectional high gainDC to DC buck converter, in accordance with various embodiments. Theunidirectional DC to DC buck converter can be derived from the aboveconverter shown in FIG. 2 by replacing switches S1 and S2 with diodes.The design details, analysis, the dynamic model of the converter and theresults given above for Buck mode operation are valid for theunidirectional DC to DC Buck converter.

Advantages of the DC-DC converter 12 over many existing DC-DC convertersincludes:

-   -   (i) In boost mode that is energy transfer form low voltage        source to high voltage-side load, a voltage gain of 5.8 and        higher is achieved. This is much higher than many existing DC-DC        converters.    -   (ii) The DC-DC converter 12 can transfer energy from high        voltage-side load to low voltage-side source during regeneration        and the proposed converter operates in buck mode, and can give a        voltage step down or Buck ratio of 1/5.8, which is a high        reduction ratio compared to many existing DC-DC converters.    -   (iii) The DC-DC converter 12 has fewer switches and passive        elements compared to existing high gain DC-DC converters.    -   (iv) The DC-DC converter 12 does not apply abnormal or extremely        high voltages or currents across the switches, as verified        analytically and through simulation.    -   (v) The current drawn from the power source is continuous and        exhibits less ripple than many existing DC-DC converters, which        is a relevant improvement for battery-powered systems. Many        existing DC-DC converters either draw discontinuous power or        cause a high ripple current from the source.    -   (vi) The DC-DC converter 12 can use a common ground between        input and output. For controllability, stability and        reliability, common ground is preferable for a bi-directional        converter.    -   (vii) The total current drawn from a low voltage source is split        between two inductors, resulting in a low current rating across        the inductors in the DC-DC converter 12 as compared to many        existing high gain converters.    -   (viii) The high voltage side is configured as a switched        capacitor arrangement which brings the ESR of capacitors in        parallel, thus reducing the negative effects of parasitic        elements.

Through analytical methods it is shown that the inductors and capacitorshave no significant influence on gain in boost mode, and the smallsignal model of the DC-DC converter 12 is presented and verified throughsimulation.

Various computational methods discussed above may be performed inconjunction with or using a computer or other processor having hardware,software, and/or firmware. The various method steps may be performed bymodules, and the modules may comprise any of a wide variety of digitaland/or analog data processing hardware and/or software arranged toperform the method steps described herein. The modules optionallycomprising data processing hardware adapted to perform one or more ofthese steps by having appropriate machine programming code associatedtherewith, the modules for two or more steps (or portions of two or moresteps) being integrated into a single processor board or separated intodifferent processor boards in any of a wide variety of integrated and/ordistributed processing architectures. These methods and systems willoften employ a tangible media embodying machine-readable code withinstructions for performing the method steps described above. Suitabletangible media may comprise a memory (including a volatile memory and/ora non-volatile memory), a storage media (such as a magnetic recording ona floppy disk, a hard disk, a tape, or the like; on an optical memorysuch as a CD, a CD-R/W, a CD-ROM, a DVD, or the like; or any otherdigital or analog storage media), or the like.

The particulars shown herein are by way of example and for purposes ofillustrative discussion of the preferred embodiments of the presentinvention only and are presented in the cause of providing what isbelieved to be the most useful and readily understood description of theprinciples and conceptual aspects of various embodiments of theinvention. In this regard, no attempt is made to show structural detailsof the invention in more detail than is necessary for the fundamentalunderstanding of the invention, the description taken with the drawingsand/or examples making apparent to those skilled in the art how theseveral forms of the invention may be embodied in practice.

The following definitions and explanations are meant and intended to becontrolling in any future construction unless clearly and unambiguouslymodified in the following examples or when application of the meaningrenders any construction meaningless or essentially meaningless. Incases where the construction of the term would render it meaningless oressentially meaningless, the definition should be taken from Webster'sDictionary, 3rd Edition or a dictionary known to those of skill in theart, such as the Oxford Dictionary of Biochemistry and Molecular Biology(Ed. Anthony Smith, Oxford University Press, Oxford, 2004).

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words ‘comprise’, ‘comprising’, and thelike are to be construed in an inclusive sense as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to”. Words using the singular or pluralnumber also include the plural and singular number, respectively.Additionally, the words “herein,” “above,” and “below” and words ofsimilar import, when used in this application, shall refer to thisapplication as a whole and not to any particular portions of theapplication.

The description of embodiments of the disclosure is not intended to beexhaustive or to limit the disclosure to the precise form disclosed.While the specific embodiments of, and examples for, the disclosure aredescribed herein for illustrative purposes, various equivalentmodifications are possible within the scope of the disclosure, as thoseskilled in the relevant art will recognize.

All references, including patent filings (including patents, patentapplications, and patent publications), scientific journals, books,treatises, technical references, and other publications and materialsdiscussed in this application, are incorporated herein by reference intheir entirety for all purposes.

Aspects of the disclosure can be modified, if necessary, to employ thesystems, functions, and concepts of the above references and applicationto provide yet further embodiments of the disclosure. These and otherchanges can be made to the disclosure in light of the detaileddescription.

Specific elements of any foregoing embodiments can be combined orsubstituted for elements in other embodiments. Furthermore, whileadvantages associated with certain embodiments of the disclosure havebeen described in the context of these embodiments, other embodimentsmay also exhibit such advantages, and not all embodiments neednecessarily exhibit such advantages to fall within the scope of thedisclosure.

While the above provides a full and complete disclosure of exemplaryembodiments of the present invention, various modifications, alternateconstructions and equivalents may be employed as desired. Consequently,although the embodiments have been described in some detail, by way ofexample and for clarity of understanding, a variety of modifications,changes, and adaptations will be obvious to those of skill in the art.Accordingly, the above description and illustrations should not beconstrued as limiting the invention, which can be defined by theappended claims.

Other variations are within the spirit of the present disclosure. Thus,while the disclosed techniques are susceptible to various modificationsand alternative constructions, certain illustrated embodiments thereofare shown in the drawings and have been described above in detail. Itshould be understood, however, that there is no intention to limit thedisclosure to the specific form or forms disclosed, but on the contrary,the intention is to cover all modifications, alternative constructionsand equivalents falling within the spirit and scope of the disclosure,as defined in the appended claims.

The use of the terms “a” and “an” and “the” and similar referents in thecontext of describing the disclosed embodiments (especially in thecontext of the following claims) are to be construed to cover both thesingular and the plural, unless otherwise indicated herein or clearlycontradicted by context. The terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (i.e., meaning“including, but not limited to,”) unless otherwise noted. The term“connected” is to be construed as partly or wholly contained within,attached to, or joined together, even if there is something intervening.Recitation of ranges of values herein are merely intended to serve as ashorthand method of referring individually to each separate valuefalling within the range, unless otherwise indicated herein and eachseparate value is incorporated into the specification as if it wereindividually recited herein. All methods described herein can beperformed in any suitable order unless otherwise indicated herein orotherwise clearly contradicted by context. The use of any and allexamples, or exemplary language (e.g., “such as”) provided herein, isintended merely to better illuminate embodiments of the disclosure anddoes not pose a limitation on the scope of the disclosure unlessotherwise claimed. No language in the specification should be construedas indicating any non-claimed element as essential to the practice ofthe disclosure.

Disjunctive language such as the phrase “at least one of X, Y, or Z,”unless specifically stated otherwise, is intended to be understoodwithin the context as used in general to present that an item, term,etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y,and/or Z). Thus, such disjunctive language is not generally intended to,and should not, imply that certain embodiments require at least one ofX, at least one of Y, or at least one of Z to each be present.

Preferred embodiments of this disclosure are described herein, includingthe best mode known to the inventors for carrying out the disclosure.Variations of those preferred embodiments may become apparent to thoseof ordinary skill in the art upon reading the foregoing description. Theinventors expect skilled artisans to employ such variations asappropriate and the inventors intend for the disclosure to be practicedotherwise than as specifically described herein. Accordingly, thisdisclosure includes all modifications and equivalents of the subjectmatter recited in the claims appended hereto as permitted by applicablelaw. Moreover, any combination of the above-described elements in allpossible variations thereof is encompassed by the disclosure unlessotherwise indicated herein or otherwise clearly contradicted by context.

1. A bi-directional direct current (DC) voltage converter, comprising: alow-voltage side ground node and a low-voltage side positive node forcoupling with a low-voltage direct current (DC) power assembly; ahigh-voltage side ground node and a high-voltage side positive node forcoupling with a high-voltage DC electrical assembly; a first inductorconnected between the low-voltage side positive node and a first circuitnode; a first switch with a first antiparallel diode across the firstswitch connected between the first circuit node and ground; a secondinductor connected between the low-voltage side positive node and asecond circuit node; a second switch with a second antiparallel diodeacross the second switch connected between the second circuit node andground; a third switch with a third antiparallel diode across the thirdswitch connected between the first circuit node and a third circuitnode; a fourth switch with a fourth antiparallel diode across the fourthswitch connected between the third circuit node and a fourth circuitnode; a first capacitor connected between the first circuit node and thefourth circuit node; a second capacitor connected between the thirdcircuit node and the second circuit node; a fifth switch with a fifthantiparallel diode across the fifth switch connected between the fourthcircuit node and the high-voltage side positive node; and a control unitoperatively coupled with each of the first switch, the second switch,the third switch, the fourth switch, and the fifth switch, wherein thecontrol unit is configured to: operate in a boost mode in which thecontrol unit controls each of the first switch, the second switch, thethird switch, the fourth switch, and the fifth switch to convert a firstlow-voltage DC power supplied by the low-voltage DC power assembly to afirst high-voltage DC power supplied to the high-voltage DC electricalassembly; wherein the first high-voltage DC power has a firsthigh-voltage potential relative to ground, wherein the first low-voltageDC power has a first low-voltage potential relative to ground, andwherein the first high-voltage potential is higher than the firstlow-voltage potential; and operate in a buck mode in which the controlunit controls each of the first switch, the second switch, the thirdswitch, the fourth switch, and the fifth switch to convert a secondhigh-voltage DC power supplied by the high-voltage DC electricalassembly to a second low-voltage DC power supplied to the low-voltage DCpower assembly; wherein the second high-voltage DC power has a secondhigh-voltage potential relative to ground, wherein the secondlow-voltage DC power has a second low-voltage potential relative toground, and wherein the second high-voltage potential is higher than thesecond low-voltage potential.
 2. The bi-directional DC voltage converterof claim 1, wherein the first high-voltage potential is at least 5 timesthe first low-voltage potential.
 3. The bi-directional DC voltageconverter of claim 1, wherein the control unit, when operated in theboost mode, is configured to keep each of the third switch, the fourthswitch, and the fifth switch open while controlling switching of each ofthe first switch and the second switch to alternate between a firstconfiguration in which the first switch is closed and the second switchis open and a second configuration in which the first switch is open andthe second switch is closed.
 4. The bi-directional DC voltage converterof claim 3, wherein the control unit, when operated in the buck mode, isconfigured to keep each of the first switch and the second switch openwhile controlling switching of each of the third switch, the fourthswitch, and the fifth switch to alternate between a third configurationin which the fourth switch is closed and each of the third switch andthe fifth switch is open and a fourth configuration in which the fourthswitch is open and each of the third switch and the fifth switch isclosed.
 5. The bi-directional DC voltage converter of claim 1, whereinthe control unit, when operated in the buck mode, is configured to keepeach of the first switch and the second switch open while controllingswitching of each of the third switch, the fourth switch, and the fifthswitch to alternate between a third configuration in which the fourthswitch is closed and each of the third switch and the fifth switch isopen and a fourth configuration in which the fourth switch is open andeach of the third switch and the fifth switch is closed.
 6. Thebi-directional DC voltage converter of claim 1, wherein the low-voltageDC power assembly comprises a rechargeable battery.
 7. Thebi-directional DC voltage converter of claim 1, wherein the high-voltageDC electrical assembly comprises an electrical motor drive.
 8. Anelectric vehicle comprising the bi-directional DC voltage converter ofclaim
 1. 9. The bi-directional DC voltage converter of claim 1, whereineach of the low-voltage side ground node and the high-voltage sideground node is connected to ground.
 10. The bi-directional DC voltageconverter of claim 1, wherein the second high-voltage potential is atleast 5 times the second low-voltage potential.
 11. The bi-directionalDC voltage converter of claim 1, further comprising a first diode, asecond diode, a third diode, a fourth diode, and a fifth diode, wherein:the first diode is connected between the first circuit node and groundand blocks flow of current through the first diode from the firstcircuit node to ground; the second diode is connected between the secondcircuit node and ground and blocks flow of current through the seconddiode from the second circuit node to ground; the third diode isconnected between the first circuit node and the third circuit node andblocks flow of current through the third diode from the third circuitnode to the first circuit node; the fourth diode is connected betweenthe third circuit node and the fourth circuit node and blocks flow ofcurrent through the fourth diode from the third circuit node to thefirst circuit node; and the fifth diode is connected between the fourthcircuit node and the high-voltage side positive node and blocks flow ofcurrent through the fifth diode from the high-voltage side positive nodeto the fourth circuit node.
 12. The bi-directional DC voltage converterof claim 1, further comprising a high-voltage side capacitor connectedbetween the high-voltage side positive node and the high-voltage sideground node.
 13. The bi-directional DC voltage converter of claim 1,further comprising a low-voltage side capacitor connected between thelow-voltage side positive node and the low-voltage side ground node. 14.A step-up direct current (DC) voltage converter, comprising: alow-voltage side ground node and a low-voltage side positive node forcoupling with a low-voltage direct current (DC) power assembly, whereinthe low-voltage side ground node is connected to ground; a high-voltageside ground node and a high-voltage side positive node for coupling witha high-voltage DC electrical assembly, wherein the high-voltage sideground node is connected to ground; a first inductor connected betweenthe low-voltage side positive node and a first circuit node; a firstswitch connected between the first circuit node and ground; a firstdiode connected between the first circuit node and ground, wherein thefirst diode blocks flow of current through the first diode from thefirst circuit node to ground; a second inductor connected between thelow-voltage side positive node and a second circuit node; a secondswitch connected between the second circuit node and ground; a seconddiode connected between the second circuit node and ground, wherein thesecond diode blocks flow of current through the second diode from thesecond circuit node to ground; a third diode connected between the firstcircuit node and a third circuit node, wherein the third diode blocksflow of current through the third diode from the third circuit node tothe first circuit node; a fourth diode connected between the thirdcircuit node and a fourth circuit node, wherein the fourth diode blocksflow of current through the fourth diode from the third circuit node tothe first circuit node; a first capacitor connected between the firstcircuit node and the fourth circuit node; a second capacitor connectedbetween the third circuit node and the second circuit node; a fifthdiode connected between the fourth circuit node and the high-voltageside positive node, wherein the fifth diode and blocks flow of currentthrough the fifth diode from the high-voltage side positive node to thefourth circuit node; and a control unit configured to control each ofthe first switch and the second switch to convert a low-voltage DC powerto a high-voltage DC power, wherein the high-voltage DC power has ahigh-voltage potential relative to ground, wherein the low-voltage DCpower has a low-voltage potential relative to ground, and wherein thehigh-voltage potential is higher than the low-voltage potential.
 15. Thestep-up DC voltage converter of claim 14, wherein the high-voltagepotential is at least 5 times the low-voltage potential.
 16. The step-upDC voltage converter of claim 14, wherein the control unit is controlswitching of each of the first switch and the second switch to alternatebetween a first configuration in which the first switch is closed andthe second switch is open and a second configuration in which the firstswitch is open and the second switch is closed.
 17. An electric vehiclecomprising the step-up DC voltage converter of claim
 14. 18. A step-downdirect current (DC) voltage converter, comprising: a low-voltage sideground node and a low-voltage side positive node for coupling with alow-voltage direct current (DC) power assembly, wherein the low-voltageside ground node is connected to ground; a high-voltage side ground nodeand a high-voltage side positive node for coupling with a high-voltageDC electrical assembly, wherein the high-voltage side ground node isconnected to ground; a first inductor connected between the low-voltageside positive node and a first circuit node; a first diode connectedbetween the first circuit node and ground, wherein the first diodeblocks flow of current through the first diode from the first circuitnode to ground; a second inductor connected between the low-voltage sidepositive node and a second circuit node; a second diode connectedbetween the second circuit node and ground, wherein the second diodeblocks flow of current through the second diode from the second circuitnode to ground; a first switch connected between the first circuit nodeand a third circuit node; a third diode connected between the firstcircuit node and a third circuit node, wherein the third diode blocksflow of current through the third diode from the third circuit node tothe first circuit node; a second switch connected between the thirdcircuit node and a fourth circuit node; a fourth diode connected betweenthe third circuit node and a fourth circuit node, wherein the fourthdiode blocks flow of current through the fourth diode from the thirdcircuit node to the first circuit node; a first capacitor connectedbetween the first circuit node and the fourth circuit node; a secondcapacitor connected between the third circuit node and the secondcircuit node; a third switch connected between the fourth circuit nodeand the high-voltage side positive node; a fifth diode connected betweenthe fourth circuit node and the high-voltage side positive node, whereinthe fifth diode and blocks flow of current through the fifth diode fromthe high-voltage side positive node to the fourth circuit node; and acontrol unit configured to control each of the first switch, the secondswitch, and the third switch to convert a high-voltage DC power to alow-voltage DC power, wherein the high-voltage DC power has ahigh-voltage potential relative to ground, wherein the low-voltage DCpower has a low-voltage potential relative to ground, and wherein thehigh-voltage potential is higher than the low-voltage potential.
 19. Thestep-down DC voltage converter of claim 18, wherein the high-voltagepotential is at least 5 times the low-voltage potential.
 20. Thestep-down DC voltage converter of claim 18, wherein the control unitcontrols switching of each of the first switch, the second switch, andthe third switch to alternate between a first configuration in which thesecond switch is closed and each of the first switch and the thirdswitch is open and a second configuration in which the second switch isopen and each of the first switch and the third switch is closed.